Design and Implementation of a Tickless Plan Based CPU Scheduler for HPC

worked on by: Paul Raatschen

Outline

Design and Implementation of a Tickless Plan based CPU scheduler for linux HPC nodes, based on previous work by Kelvin Glaß.
Detailed outline can be found in the expose

Thesis Requirements

• Implement a loadable kernel module for the Linux kernel, that allowed the execution of plan based tasks.
  • Set up Instruction counter events for each thread/process in the execution plan.
  • Issue rescheduling upon an instruction counter overflow event
  • Transfer required execution plan information to the sched_ext scheduler
• Implement a loadable scheduler based on sched_ext, that schedules a thread/process according to its execution plan
• Test the functionality of kernel module + scheduler in a realistic setup

Milestones and Planning

A milestone is a scheduled event signifying the completion of a major deliverable or a set of related deliverables. A milestone has zero duration and no effort -- there is no work associated with a milestone. It is a flag in the workplan to signify some other work has completed. Usually a milestone is used as a project checkpoint to validate how the project is progressing and revalidate work. (Source: http://www.mariosalexandrou.com/definition/milestone.asp)

Milestone no.	Past		CW	Goals	accomplished
1		5	CW23	Setup development environment	accomplished
2		5	CW24	Implement kernel module prototype	pending

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Weekly Status

Week 1 (CW 23)

Activities

• Setup a development environment using a qemu VM with Ubuntu Server 25.04
• Build a custom linux kernel (v6.15) configured for tickless scheduling (no_hz_full)
• Build and load a "hello world" kernel module for the custom kernel
• Run Ubuntu Server 25.04 with custom kernel in qemu VM

Results

• achieved all goals

Next Steps

• Development of the kernel module

Problems

• ...
  
  

Week 2 (CW 24)

Activities

• Develop a prototype for the kernel module

Results

• …

Next Steps

• …

Problems

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